6

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L512L18P_2.p65 – Rev. 6/01

©2001, Micron Technology, Inc.

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

TQFP PIN DESCRIPTIONS

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

37

37

SA0

Input

Synchronous Address Inputs: These inputs are registered

36

36

SA1

and must meet the setup and hold times around the rising

32-35, 44-50,

32-35, 44-50,

SA

edge of CLK. Pin 84 is reserved as an address bit for

80-83, 99, 100

81-83, 99, 100

higher-density 18Mb ZBT SRAMs. SA0 and SA1 are the

two least significant bits (LSB) of the address field and

set the internal burst counter if burst is desired.

93

93

BWa#

Input

Synchronous Byte Write Enables: These active LOW inputs

94

94

BWb#

allow individual bytes to be written when a WRITE cycle is

–

95

BWc#

active and must meet the setup and hold times around the

–

96

BWd#

rising edge of CLK. BYTE WRITEs need to be asserted on

the same cycle as the address. BWs are associated with

addresses and apply to subsequent data. BWa# controls

DQa pins; BWb# controls DQb pins; BWc# controls DQc

pins; BWd# controls DQd pins.

89

89

CLK

Input

Clock: This signal registers the address, data, chip enables,

byte write enables, and burst control inputs on its rising

edge. All synchronous inputs must meet setup and hold

times around the clock’s rising edge.

98

98

CE#

Input

Synchronous Chip Enable: This active LOW input is used to

enable the device and is sampled only when a new

external address is loaded (ADV/LD# is LOW).

92

92

CE2#

Input

Synchronous Chip Enable: This active LOW input is used to

enable the device and is sampled only when a new

external address is loaded (ADV/LD# is LOW). This

input can be used for memory depth expansion.

97

97

CE2

Input

Synchronous Chip Enable: This active HIGH input is used to

enable the device and is sampled only when a new

external address is loaded (ADV/LD# is LOW). This

input can be used for memory depth expansion.

86

86

OE#

Input

Output Enable: This active LOW, asynchronous input

(G#)

enables the data I/O output drivers. G# is the JEDEC-

standard term for OE#.

85

85

ADV/LD# Input

Synchronous Address Advance/Load: When HIGH, this

input is used to advance the internal burst counter,

controlling burst access after the external address is

loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW

on ADV/LD# clocks a new address at the CLK rising edge.

87

87

CKE#

Input

Synchronous Clock Enable: This active LOW input permits

CLK to propagate throughout the device. When CKE# is

HIGH, the device ignores the CLK input and effectively

internally extends the previous CLK cycle. This input must

meet setup and hold times around the rising edge of CLK.

64

64

ZZ

Input

Snooze Enable: This active HIGH, asynchronous input

causes the device to enter a low-power standby mode in

which all data in the memory array is retained. When ZZ is

active, all other inputs are ignored.

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