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S11961-01CR Datasheet(PDF) 6 Page - Hamamatsu Corporation

Part # S11961-01CR
Description  Distance linear image sensor
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Manufacturer  HAMAMATSU [Hamamatsu Corporation]
Direct Link  http://www.hamamatsu.com
Logo HAMAMATSU - Hamamatsu Corporation

S11961-01CR Datasheet(HTML) 6 Page - Hamamatsu Corporation

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6
Distance linear image sensor
S11961-01CR
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master clock pulse duty ratio
-
45
50
55
%
Master clock pulse rise and fall times
tr(mclk), tf(mclk)
0
-
20
ns
Pixel reset pulse high period
thp(p_res)
10
-
-
μs
Pixel reset pulse rise and fall times
tr(p_res), tf(p_res)
0
-
20
ns
Signal sampling pulse high period
thp(phic)
1
-
-
μs
Signal sampling pulse rise and fall times
tr(phic), tf(phic)
0
-
20
ns
Signal readout trigger pulse rise and fall times
tr(trig), tf(trig)
0
-
20
ns
Time from rising edge of master clock pulse to pixel
reset pulse
t0
0
-
-
ns
Time from rising edge of pixel reset pulse to rising
edge of signal sampling pulse
t1
1
-
-
μs
Time from falling edge of signal sampling pulse to
rising edge of signal readout trigger pulse
t2
1.2
-
-
μs
Time from rising edge of master clock pulse to rising
edge of signal readout trigger pulse
t3
1/4 × 1/f(mclk)
-
1/2 × 1/f(mclk)
s
Time from rising edge of signal readout trigger pulse
to rising edge of master clock pulse
t4
1/4 × 1/f(mclk)
-
1/2 × 1/f(mclk)
s
Time from rising edge of master clock pulse to falling
edge of signal readout trigger pulse
t5
1/4 × 1/f(mclk)
-
1/2 × 1/f(mclk)
s
Time from falling edge of signal readout trigger pulse
to rising edge of master clock pulse
t6
1/4 × 1/f(mclk)
-
1/2 × 1/f(mclk)
s
Time from rising edge of master clock pulse (after
reading signals from all pixels) to rising edge of
output signal sampling pulse
t7
1/f(mclk)
-
-
s
Time from rising edge of master clock pulse (after
reading signals from all pixels) to rising edge of pixel
reset pulse
t8
1/f(mclk)
-
-
s
Time from rising edge of master clock pulse to falling
edge of output signal synchronous pulse*7
td(dclk)
0
25
50
ns
Output signal synchronous pulse output voltage rise
time (10 to 90%)*7
tr(dclk)
-
20
40
ns
Output signal synchronous pulse output voltage fall
time (10 to 90%)*7
tf(dclk)
-
20
40
ns
Settling time of output signal 1, 2 (10 to 90%)*7 *8
tr(Vout), tf(Vout)
-
35
70
ns
Time from rising edge of master clock pulse to output
signal 1, 2 (output 50%)*7
td(Vout)
-
40
80
ns
Charge transfer clock pulse interval
tpi(VTX)
60
-
-
ns
Charge transfer clock pulse (VTX1) high period
thp(VTX1)
30
-
-
ns
Charge transfer clock pulse (VTX1) low period
tlp(VTX1)
-
tpi(VTX) -
thp(VTX2) -
thp(VTX3)
-ns
Charge transfer clock pulse (VTX2) high period
thp(VTX2)
30
-
-
ns
Charge transfer clock pulse (VTX2) low period
tlp(VTX2)
-
tpi(VTX) -
thp(VTX1) -
thp(VTX3)
-ns
Charge transfer clock pulse (VTX3) high period
thp(VTX3)
0
-
-
ns
Charge transfer clock pulse (VTX3) low period
tlp(VTX3)
-
tpi(VTX) -
thp(VTX1) -
thp(VTX2)
-ns
Charge transfer clock pulse voltage rise time
tr(VTX)
-
3
-
ns
Charge transfer clock pulse voltage fall time
tf(VTX)
-
3
-
ns
Charge transfer clock pulse voltage
High level
VTX1, VTX2, VTX3
-3-
V
Low level
-
0
-
V
Time from rising edge of signal readout trigger pulse
to start VTX operation
t9
1/f(mclk)
-
-
s
Time from finish VTX operation to rising edge of
output signal synchronous pulse
t10
1/f(mclk)
-
-
s
Time from finish VTX operation to rising edge of pixel
reset pulse
t11
1/f(mclk)
-
-
s
*7: CL=3 pF
*8: Output voltage=0.1 V


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