Distance area image sensor

S11962-01CR

6

Parameter

Symbol

Min.

Typ.

Max.

Unit

Master clock pulse duty ratio

-

45

50

55

%

Master clock pulse rise and fall times

tr(mclk), tf(mclk)

0

-

20

ns

Frame reset pulse rise and fall times

tr(reset), tf(reset)

0

-

20

ns

Frame synchronous trigger pulse rise and fall times

tr(vst), tf(vst)

0

-

20

ns

Line synchronous trigger pulse rise and fall times

tr(hst), tf(hst)

0

-

20

ns

Pixel reset pulse rise and fall times

tr(ext_res), tf(ext_res)

0

-

20

ns

Time from falling edge of master clock pulse to rising

edge of frame reset pulse

t1

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from rising edge of frame reset pulse to falling

edge of master clock pulse

t2

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of master clock pulse to falling

edge of frame reset pulse

t3

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of frame reset pulse to falling

edge of master clock pulse

t4

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of master clock pulse to rising

edge of frame synchronous trigger pulse

t5

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from rising edge of frame synchronous trigger

pulse to falling edge of master clock pulse

t6

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of master clock pulse to falling

edge of frame synchronous trigger pulse

t7

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of frame synchronous trigger

pulse to falling edge of master clock pulse

t8

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from rising edge of master clock pulse to rising

edge of line synchronous trigger pulse

t9

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from rising edge of line synchronous trigger pulse

to rising edge of master clock pulse

t10

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from rising edge of master clock pulse to falling

edge of line synchronous trigger pulse

t11

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of line synchronous trigger

pulse to rising edge of master clock pulse

t12

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Readout time

t13

(110/f(mclk) + t15)

× 72 + t18 + t19

--

s

Integration time

t14

-

10

-

ms

Time from rising edge of master clock pulse (after reading signals

from all pixels) to rising edge of master clock pulse (hst: high period)

t15

10/f(mclk)

-

-

s

Time from falling edge of master clock pulse to rising

edge of output signal synchronous pulse

td(dclk)

0

25

50

ns

Output signal synchronous pulse output voltage rise time

tr(dclk)

-

20

40

ns

Output signal synchronous pulse output voltage fall

tf(dclk)

-

20

40

ns

Time from rising edge of master clock pulse to rising

edge of output signal effective period pulse

td(oe)

0

25

50

ns

Output signal effective period pulse rise time

tr(oe)

-

20

40

ns

Output signal effective period pulse fall time

tf(oe)

-

20

40

ns

tr(Vout), tf(Vout)

-

35

70

ns

Time from rising edge of master clock pulse to output

td(Vout)

-

40

80

ns

*8: Output voltage=0.1 V