Distance area image sensor

S11963-01CR

6

Parameter

Symbol

Min.

Typ.

Max.

Unit

Master clock pulse duty ratio

-

45

50

55

%

Master clock pulse rise and fall times

tr(mclk), tf(mclk)

0

-

20

ns

Frame reset pulse rise and fall times

tr(reset), tf(reset)

0

-

20

ns

Frame synchronous trigger pulse rise and fall times

tr(vst), tf(vst)

0

-

20

ns

Line synchronous trigger pulse rise and fall times

tr(hst), tf(hst)

0

-

20

ns

Pixel reset pulse high period

thp(ext_res)

10

-

-

μs

Pixel reset pulse rise and fall times

tr(ext_res), tf(ext_res)

0

-

20

ns

Time from falling edge of master clock pulse to rising

edge of pixel reset pulse

t1

1/4 × 1/f(mclk)

-

-

s

Time from rising edge of pixel reset pulse to falling edge

of frame reset pulse

t2

0

--

s

Time from falling edge of pixel reset pulse to falling

edge of master clock pulse

t3

1/4 × 1/f(mclk)

-

-

s

Time from falling edge of master clock pulse to rising

edge of frame reset pulse

t4

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from rising edge of frame reset pulse to falling

edge of master clock pulse

t5

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of master clock pulse to falling

edge of frame reset pulse

t6

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of frame reset pulse to falling

edge of master clock pulse

t7

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of master clock pulse to rising

edge of frame synchronous trigger pulse

t8

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from rising edge of frame synchronous trigger

pulse to falling edge of master clock pulse

t9

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of master clock pulse to falling

edge of frame synchronous trigger pulse

t10

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of frame synchronous trigger

pulse to falling edge of master clock pulse

t11

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from rising edge of master clock pulse to rising

edge of line synchronous trigger pulse

t12

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from rising edge of line synchronous trigger pulse

to rising edge of master clock pulse

t13

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from rising edge of master clock pulse to falling

edge of line synchronous trigger pulse

t14

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Time from falling edge of line synchronous trigger

pulse to rising edge of master clock pulse

t15

1/4 × 1/f(mclk)

-

1/2 × 1/f(mclk)

s

Reset level readout time

t16

{208/f(mclk) + t20} ×

128 + thp(ext_res) + t3

--

s

Integration time

t17

-

10

-

ms

Integration signal readout time

t18

{208/f(mclk) + t20} ×

128 + {1/2 × 1/f(mclk)}

--

s

Time from falling edge of line synchronous pulse (last

pulse) to “VTX enable period=on”

t19

0

s

Time from “VTX enable period=off” to falling edge of

frame reset pulse

t20

0

s

Time from rising edge of master clock pulse (after reading from

all pixels) to rising edge of master clock pulse (hst: High period)

t21

10/f(mclk)

s

Time from falling edge of master clock pulse to rising

td(dclk)

0

25

50

ns

Rise time of output signal synchronous pulse output

tf(dclk)

-

20

40

ns

Fall time of output signal synchronous pulse output

tf(dclk)

-

20

40

ns