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ML4830 Datasheet(PDF) 6 Page - Micro Linear Corporation |
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ML4830 Datasheet(HTML) 6 Page - Micro Linear Corporation |
6 / 15 page ![]() ML4830 6 The output of the gain modulator appears as a voltage across the 14K resistor (Figure 1) on the positive terminal of IA to form the reference for the current error amplifier. When the loop is in regulation, the negative voltage on IA+/I(LIM) (Pin 4) keeps the positive terminal of IA at 0V. V I SINE VEA k MUL ≈× × − × Ω 0 034 1 1 14 .( ) ( . ) ( ) (1) where: I(SINE) is the current in the dropping resistor, V(EA) is the output of the error amplifier (Pin 20). The output of the gain modulator is limited to 0.88V. AVERAGE CURRENT AND OUTPUT VOLTAGE REGULATION The PWM regulator in the PFC Control section will act to offset the positive voltage caused by the multiplier output by producing an offsetting negative voltage on the current sense resistor at Pin 4. A cycle-by-cycle current limit is included to protect the MOSFET from high speed current transients. When the voltage at Pin 4 goes negative by more than 1V, the PFC cycle is terminated. For more information on compensating the average current and boost voltage error amplifier loops, see Application Note 16 . Figure 1. ML4830 Block Diagram 12 R(X)/C(X) INTERRUPT VCC VREF GND OVP/INHIBIT IA OUT IA – IA+/ I(LIM) I(SINE) EA OUT EA – 10 17 18 13 11 2 1 4 3 20 19 OUT B 14 + – + – + – + – – + + – – + – + – + VREF VREF 5V 6.8V 2.6V –1V PREHEAT AND INTERRUPT TIMER UNDER-VOLTAGE AND THERMAL SHUTDOWN IA 14K A1 2.5V + – I(LIM) EA LFB OUT S R Q S R Q T Q Q PWM VCO–O OUT A 15 PFC OUT 16 R(T)/C(T) 9 R(SET) IR(SET) 7 LAMP F.B. 5 MODE 8 LFB OUT 6 OSCILLATOR LOGIC VCO–O PWM CLK INH GAIN MODULATORS OVERVOLTAGE PROTECTION AND INHIBIT The OVP/INHIBIT pin serves to protect the power circuit from being subjected to excessive voltages if the load should change suddenly (lamp removal). A divider from the high voltage DC bus (Figure 8: R14, R24) sets the OVP trip level. When the voltage on Pin 11 exceeds 5V, the PFC transistor is inhibited. The ballast section will continue to operate. If Pin 11 is driven above 6.8V, the IC is inhibited and goes into the low quiescent mode. The OVP threshold should be set to a level where the power components are safe to operate, but not so low as to interfere with the boost voltage regulation loop (R11, R12, R23). BALLAST OUTPUT SECTION The IC controls output power to the lamps in one of three different modes. The Mode pin (Pin 8) sets the operating mode of the IC. With Pin 8 at GND, the output section is in the Frequency Modulation mode with non-overlapping conduction, which means that both ballast output drivers will be low during tDIS (Figure 2). In the overlapping mode (VCO-O), Pin 8 is left open and the transition from OUT A high to OUT B high occurs with no dead time. This mode is typically used in current fed ballast topologies. |
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