TPS5120

DUAL OUTPUT, TWOPHASE SYNCHRONOUS BUCK DC/DC CONTROLLER

SLVS278E – AUGUST 2000 – REVISED MARCH 2003

7

POST OFFICE BOX 655303

Table 1. Logic Chart

5V_STBY

STBY1

STBY2

SMPS1

SMPS2

5 V REGULATOR

POWERGOOD

L

L

L

Disable

Disable

Disable

Disable

L

L

H

Disable

Enable

Enable

Active†

L

H

L

Enable

Disable

Enable

Active†

L

H

H

Enable

Enable

Enable

Active

H

L

L

Disable

Disable

Enable

L

H

L

H

Disable

Enable

Enable

Active†

H

H

L

Enable

Disable

Enable

Active†

H

H

H

Enable

Enable

Enable

Active

† PG is set high during a softstart.

POWERGOOD timing sequence

POWERGOOD

STBY1

STBY2

INV1

INV2

H

L

H

L

H

L

0.91 V

0.85 V

0.78 V

0 V

0.91 V

0.85 V

0.78 V

0 V

TSS

During a softstart, this channel’s powergood comparator output is fixed low (POWERGOOD output is high).