TPS5120

DUAL OUTPUT, TWOPHASE SYNCHRONOUS BUCK DC/DC CONTROLLER

SLVS278E – AUGUST 2000 – REVISED MARCH 2003

5

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

TRIP2

23

I

External resistor connection for CH2 output current control

VCC

24

Supply voltage input

VREF5

22

O

5-V internal regulator output

5V_STBY

6

I

5-V linear regulator control

detailed description

switching-mode power supply (SMPS) 1, 2

TPS5120 includes dual SMPS controllers that operate 180

° out of phase and at the same frequency. Both

channels have standby and softstart.

5-V regulator

An internal linear voltage regulator is used for the high-side driver bootstrap voltage and source of VREF

(0.85 V). When the 5-V regulator is disconnected from the MOSFET drivers, it is only used for the source of

VREF. Since the input voltage range is from 4.5 V to 28 V, this feature offers a fixed voltage for the bootstrap

voltage so that the drive design is much easier. It is also used for powering the low-side driver. The tolerance

is 4%. The 5-V regulator is disabled when STBY1, STBY2, and 5V_STBY are all set low.

5-V switch

If the internal 5-V switch senses the 5-V input from the REG5V_IN pin, the internal 5-V linear regulator is

disconnected from the MOSFET drivers. The external 5 V is then used for both the low-side driver and the

high-side bootstrap, thus, increasing the efficiency.

error amplifier

Each channel has its own error amplifier to regulate the output voltage of the synchronous buck converter. It

is used in the PWM mode for the high output current condition (> 0.2 A). The unity gain bandwidth is 2.5 MHz.

This decreases the amplifier delay during fast load transients and contributes to a fast transient response.

skip comparator

In skip mode, each channel has its own hysteretic comparator to regulate the output voltage of the synchronous

buck converter. The hysteresis is set internally and is typically set at 9 mV. The delay from the comparator input

to the driver output is typically 1.2

µs.

low-side driver

VREF5. The current rating of the driver is typically 1.5 A at source and sink.

high-side driver

at source and sink. When configured as a floating driver, the bias voltage to the driver is developed from VREF5,

limiting the maximum drive voltage between OUTx_u and LLx to 5 V. The maximum voltage that can be applied

between LHx and OUTGND is 33 V.

deadtime

Deadtime prevents shoot through current from flowing through the main power FETs during switching transitions

by actively controlling the turnon time of the MOSFETs drivers.