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PIC16F84A Datasheet(PDF) 12 Page - Microchip Technology |
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PIC16F84A Datasheet(HTML) 12 Page - Microchip Technology |
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12 / 124 page  PIC16F8X DS30430C-page 12 © 1998 Microchip Technology Inc. 4.2 Data Memory Organization The data memory is partitioned into two areas. The first is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. Portions of data memory are banked. This is for both the SFR area and the GPR area. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection. These control bits are located in the STATUS Register. Figure 4-1 and Figure 4-2 show the data memory map organization. Instructions MOVWF and MOVF can move values from the W register to any location in the register file (“F”), and vice-versa. The entire data memory can be accessed either directly using the absolute address of each register file or indirectly through the File Select Register (FSR) (Section 4.5). Indirect addressing uses the present value of the RP1:RP0 bits for access into the banked areas of data memory. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank 1. Each Bank extends up to 7Fh (128 bytes). The first twelve locations of each Bank are reserved for the Special Function Registers. The remainder are Gen- eral Purpose Registers implemented as static RAM. 4.2.1 GENERAL PURPOSE REGISTER FILE All devices have some amount of General Purpose Register (GPR) area. Each GPR is 8 bits wide and is accessed either directly or indirectly through the FSR (Section 4.5). The GPR addresses in bank 1 are mapped to addresses in bank 0. As an example, addressing loca- tion 0Ch or 8Ch will access the same GPR. 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (Figure 4-1, Figure 4-2 and Table 4-1) are used by the CPU and Peripheral functions to control the device operation. These registers are static RAM. The special function registers can be classified into two sets, core and peripheral. Those associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specific feature. |
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