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PIC16F84A Datasheet(PDF) 50 Page - Microchip Technology |
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PIC16F84A Datasheet(HTML) 50 Page - Microchip Technology |
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50 / 124 page  PIC16F8X DS30430C-page 50 © 1998 Microchip Technology Inc. 8.11 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT Wake-up causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming configuration bit WDTE as a '0' (Section 8.1). 8.11.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION_REG register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler (if assigned to the WDT) and prevent it from timing out and generating a device RESET condition. The TO bit in the STATUS register will be cleared upon a WDT time-out. 8.11.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT time-out occurs. FIGURE 8-18: WATCHDOG TIMER BLOCK DIAGRAM TABLE 8-7 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 2007h Config. bits (2) (2) (2) (2) PWRTE(1) WDTE FOSC1 FOSC0 (2) 81h OPTION_ REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown. Shaded cells are not used by the WDT. Note 1: See Figure 8-1 and Figure 8-2 for operation of the PWRTE bit. 2: See Figure 8-1, Figure 8-2 and Section 8.13 for operation of the Code and Data protection bits. From TMR0 Clock Source (Figure 6-6) To TMR0 (Figure 6-6) Postscaler WDT Timer M U X PSA 8 - to -1 MUX PSA WDT Time-out 1 0 0 1 WDT Enable Bit PS2:PS0 • • 8 MUX Note: PSA and PS2:PS0 are bits in the OPTION_REG register. |
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