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PIC16F84A Datasheet(PDF) 43 Page - Microchip Technology |
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PIC16F84A Datasheet(HTML) 43 Page - Microchip Technology |
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43 / 124 page  PIC16F8X © 1998 Microchip Technology Inc. DS30430C-page 43 8.4 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A minimum rise time for VDD must be met for this to operate properly. See Electrical Specifi- cations for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607, " Power-up Trouble Shooting." The POR circuit does not produce an internal reset when VDD declines. 8.5 Power-up Timer (PWRT) The Power-up Timer (PWRT) provides a fixed 72 ms nominal time-out (TPWRT) from POR (Figure 8-10, Figure 8-11, Figure 8-12 and Figure 8-13). The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT delay allows the VDD to rise to an accept- able level (Possible exception shown in Figure 8-13). A configuration bit, PWRTE, can enable/disable the PWRT. See either Figure 8-1 or Figure 8-2 for the oper- ation of the PWRTE bit for a particular device. The power-up time delay TPWRT will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details. 8.6 Oscillator Start-up Timer (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle delay (from OSC1 input) after the PWRT delay ends (Figure 8-10, Figure 8-11, Figure 8-12 and Figure 8-13). This ensures the crystal oscillator or resonator has started and stabilized. The OST time-out (TOST) is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its final value. In this case (Figure 8-13), an external power-on reset circuit may be necessary (Figure 8-9). FIGURE 8-9: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) Note 1: External Power-on Reset circuit is required only if VDD power-up rate is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k Ω is recommended to make sure that voltage drop across R does not exceed 0.2V (max leakage current spec on MCLR pin is 5 µA). A larger voltage drop will degrade VIH level on the MCLR pin. 3: R1 = 100 Ω to 1 kΩ will limit any current flowing into MCLR from external capacitor C in the event of an MCLR pin breakdown due to ESD or EOS. C R1 R D VDD MCLR PIC16FXX VDD |
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Similar Description - PIC16F84A |
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