Pin

Function

Check Bit Inputs

BPAR

Check Bit Parity Input

EV/OD

Even/Odd Parity Select

EN

Parity Enable

HOLD

Syndrome Hold Input

S-IN

Syndrome Bit Input

SHIFT

Syndrome Bit Shift

CLK

Clock Input

Parity Output

PGEN

Parity Generate Output

PARERR/PARERR

Parity Error Output

s Hamming code generation

s 8-bit wide

s Expandable for more width

s Provides parity register

s Fully compatible with industry standard 10KH,

100K ECL levels

s Internal75K

s Fully compatible with Motorola MC10E/100E193

s Available in 28-pin PLCC package

FEATURES

The SY10/100E193 are error detection and correction

(EDAC) circuits designed for use in new, high- performance

ECL systems. The E193 generates hamming parity codes

output gives the parity of the whole word. PGEN provides

word parity after Odd/Even parity control and gating with

the BPAR input. PGEN also feeds into a 1-bit shiftable

register for use as part of a scan ring.

The combinatorial part of the device generates the same

code pattern as the Motorola MC10193.

Used in conjunction with 12-bit parity generators, such

as the E160, a SECDED (single error correction, double

error detection) error system can be designed for a multiple

of an 8-bit word.

DESCRIPTION

ERROR DETECTION/

CORRECTION CIRCUIT

PIN CONFIGURATION

PIN NAMES

Rev.: C

Amendment: /1

Issue Date:

February, 1998

SY10E193

SY100E193

TOP VIEW

PLCC

J28-1

26

27

28

1

2

3

4

18

17

16

15

14

13

12

25 24 23 22 21 20 19

5

6

7

8

9

10 11

PARERR

PARERR

BPAR

EV/OD

1