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P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005

MX10EXA

NOTES:

* SFRs are bit addressable.

1. At reset, the BCR register is loaded with the binary value 0000 0a11, where "a" is the value on the BUSW pin. This

defaults the address bus size to 20 bits, Since the MX10EXA has only 20 address lines.

2. SFR is loaded from the reset vector.

3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0.

4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may

be used for other purposes in future XA derivatives. The reset value shown for these bits is 0.

5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after

reset, based on the condition found on the EA pin. Thus all PnCFGA registers will contain FF and PnCFGB

registers will contain 00. When the XA begins execution using external code memory, the default configuration for

pins that are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will

reflect this difference.

6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.

7. The MX10EXA implements an 8-bit SFR bus. All SFR accesses must be 8-bit operations.

Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return

undefined data in the upper byte.

8. The AUXR reset value is typically 00h. If the Boot Loader is activated at reset because the Flash status byte is non-

zero or because the Boot Vector has been forced (by PSEN = 0, ALE = 1, EA = 1 at reset), the AUXR reset value

will be 1x00 0000b. Bit 6 will be a 1 if the on-chip VPP generator is running and ready, otherwise it will be a 0.