TMP411-Q1

www.ti.com

SBOS527F – DECEMBER 2010 – REVISED NOVEMBER 2013

Table 11. Allowable THERM Hysteresis Val (continued)

THERM HYSTERESIS VALUE

TEMPERATURE

TH[11:4]

(°C)

(HEX)

(STANDARD BINARY)

255

1111 1111

FF

BUS OVERVIEW

The TMP411-Q1 is SMBus interface-compatible. In SMBus protocol, the device that initiates the transfer is called

a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device

that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.

To address a specific device, a START condition is initiated. START is indicated by pulling the data line (SDA)

from a high to low logic level while SCL is high. All slaves on the bus shift in the slave address byte, with the last

bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being

addressed responds to the master by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data

transfer, SDA must remain stable while SCL is high, because any change in SDA while SCL is high is interpreted

as a control signal.

Once all data has been transferred, the master generates a STOP condition. STOP is indicated by pulling SDA

from low to high while SCL is high.

Copyright © 2010–2013, Texas Instruments Incorporated

Submit Documentation Feedback

21

Product Folder Links: TMP411-Q1