M13S2561616A-2S datasheet(3/49 Pages) ESMT

Part #	M13S2561616A-2S

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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3 / 49 page

ESMT

M13S2561616A (2S)

Operation Temperature Condition -40°C~85°C

Elite Semiconductor Memory Technology Inc.

Publication Date : Jan. 2015

Revision : 1.0

3/49

PIN CONFIGURATION (TOP VIEW)

BALL CONFIGURATION (TOP VIEW)

(TSOPII 66L, 400milX875mil Body, 0.65mm Pin Pitch)

(BGA60, 8mmX13mmX1.0mm Body, 0.8mm Ball Pitch)

Pin Description

Pin Name

Function

Pin Name

Function

A0~A12,

BA0, BA1

Address inputs

- Row address A0~A12

- Column address A0~A8

A10/AP: AUTO Precharge

BA0, BA1: Bank selects (4 Banks)

LDM, UDM

DM is an input mask signal for write data.

LDM corresponds to the data on DQ0~DQ7;

UDM correspond to the data on DQ8~DQ15.

DQ0~DQ15

Data-in/Data-out

CLK, CLK

Clock input

RAS

Row address strobe

CKE

Clock enable

CAS

Column address strobe

CS

Chip select

WE

Write enable

VDDQ

Supply Voltage for DQ

VSS

Ground

VSSQ

Ground for DQ

VDD

Power

VREF

Reference Voltage for SSTL_2

LDQS, UDQS

Bi-directional Data Strobe.

LDQS corresponds to the data on DQ0~DQ7;

UDQS correspond to the data on DQ8~DQ15.

NC

No connection

VSSQ

DQ14

DQ12

DQ10

DQ8

VREF

A

B

C

D

E

F

G

H

J

K

L

M

DQ15

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

A8

A6

A4

VSS

DQ13

DQ11

DQ9

UDQS

UDM

CLK

CKE

A9

A7

A5

VSS

VDDQ

DQ1

DQ3

DQ5

DQ7

NC

VDD

DQ2

DQ4

DQ6

LDQS

LDM

WE

RAS

BA1

A0

A2

VDD

DQ0

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

CS

BA0

A10/AP

A1

A3

12

3

78

9

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