m13l2561616a-2a datasheet(21/49 Pages) ESMT

Part #	M13L2561616A-2A

Description	Double-data-rate architecture, two data transfers per clock cycle

Download	49 Pages

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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21 / 49 page

ESMT

M13L2561616A (2A)

Elite Semiconductor Memory Technology Inc.

Publication Date : Sep. 2012

Revision : 1.0

21/49

Write Interrupted by a Write

A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the

interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining

addresses are overridden by the new address and data will be written into the device until the programmed burst length is

satisfied.

01

23

4

5

6

7

8

CO M M A ND

DQ S

DQ ' s

NOP

NO P

NOP

NO P

N O P

DIN A0

WRIT E A

D IN A1

D IN B 2

DIN B3

D IN B0

DIN B1

CL K

1t CK

Hi - Z

Hi- Z

WR IT E B

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M13L2561616A-2A Datasheet(PDF) 21 Page - Elite Semiconductor Memory Technology Inc.

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