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M13L2561616A-2A Datasheet(PDF) 9 Page - Elite Semiconductor Memory Technology Inc. |
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M13L2561616A-2A Datasheet(HTML) 9 Page - Elite Semiconductor Memory Technology Inc. |
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9 / 49 page  ESMT M13L2561616A (2A) Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2012 Revision : 1.0 9/49 AC Timing Parameter & Specifications (Note: 1~ 5, 8~9) -4 -5 -6 Parameter Symbol min max min max min max Unit Note CL2 7.5 12 7.5 12 7.5 12 CL2.5 5 12 5 12 6 12 CL3 4 10 5 12 6 12 Clock period CL4 tCK 4 10 - - - - ns DQ output access time from CLK/ CLK tAC -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns CLK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CLK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQS output access time from CLK/ CLK tDQSCK -0.55 +0.55 -0.6 +0.6 -0.6 +0.6 ns Clock to first rising edge of DQS delay tDQSS 0.72 1.25 0.72 1.25 0.72 1.25 tCK DQ and DM input setup time (to DQS) tDS 0.4 0.4 0.4 ns DQ and DM input hold time (to DQS) tDH 0.4 0.4 0.4 ns DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 1.75 ns 17 Address and Control input setup time (fast) tIS 0.6 0.6 0.6 ns 14,16~ 18 Address and Control input hold time (fast) tIH 0.6 0.6 0.6 ns 14, 16~18 Address and Control input setup time (slow) tIS 0.8 0.8 0.8 ns 15~18 Address and Control input hold time (slow) tIH 0.8 0.8 0.8 ns 15~18 Control and Address input pulse width (for each input) tIPW 2.2 2.2 2.2 ns 17 DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK DQS falling edge to CLK setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge hold time from CLK tDSH 0.2 0.2 0.2 tCK Data strobe edge to output data edge tDQSQ 0.4 0.4 0.4 ns 21 Data-out high-impedance time from CLK/ CLK tHZ +0.7 +0.7 +0.7 ns 10 Data-out low-impedance time from CLK/ CLK tLZ -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns 10 Clock half period tHP tCLmin or tCHmin tCLmin or tCHmin tCLmin or tCHmin ns 19,20 DQ/DQS output hold time from DQS tQH tHP- tQHS tHP- tQHS tHP- tQHS ns 20 Data hold skew factor tQHS 0.5 0.5 0.5 ns |
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