M13L2561616A-2A datasheet(43/49 Pages) ESMT

Part #	M13L2561616A-2A

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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43 / 49 page

ESMT

M13L2561616A (2A)

Elite Semiconductor Memory Technology Inc.

Publication Date : Sep. 2012

Revision : 1.0

43/49

Power up & Initialization Sequence (based on DDR400)

VDDQ

VREF

A0 - A 9

A11 - A n

P o w e r-u p :

VD D a n d

CL K s t a b l e

BA 0 , BA 1

E x te nde d

M ode

Re g i s t e r

Se t

COMMAND

DM

DQS

t MR D

2 0 0 cyc l e s o f C L K * *

Load

Mo d e

R egi s t er

Re s e t D L L

(wi t h A 8 = H)

L oad

Mo de

R egis t er

( w ith A 8=L)

VDD

A1 0

T = 2 00us

VTT

(system*)

tVDT >=0

CLK

CKE

NOP

t CH

t CL

t CK

t IS t IH

PRE

EMRS

MRS

PRE

AR

MRS

ACT

t IH

t IS

CODE

t IH

t IS

LV C O M S L O W L EV EL

CODE

RA

t IH

t IS

CODE

RA

BA0=L,

BA1=L

BA

t IH

t IS

t IH t IS

BA0=L,

BA1=L

H i gh- Z

DQ

Hi g h - Z

t RP

t RF C

t MR D

ALL BANKS

t RF C

BA0=H,

BA1=L

t IH

t IS

:D o n ’ t c a r e

10 12 2 B 1 6 R . B

Notes:

* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.

** = tMRD is required before any command can be applied, and 200 cycles of CLK are required before an executable

command can be applied. The two Auto Refresh commands may be moved to follow the first MRS but precede the

second PRECHARGE ALL command.

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M13L2561616A-2A Datasheet(PDF) 43 Page - Elite Semiconductor Memory Technology Inc.

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