Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

Preview PDF HTML

M13L2561616A-2A Datasheet(PDF) 25 Page - Elite Semiconductor Memory Technology Inc.

Part # M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
Download  49 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

M13L2561616A-2A Datasheet(HTML) 25 Page - Elite Semiconductor Memory Technology Inc.

Back Button M13L2561616A-2A Datasheet HTML 21Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 22Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 23Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 24Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 25Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 26Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 27Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 28Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 29Page - Elite Semiconductor Memory Technology Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 25 / 49 page
background image
ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
25/49
Read With Auto Precharge
If a read with auto precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock
later from a read with auto precharge command when tRAS (min) is satisfied. If not, the start point of precharge operation will be
delayed until tRAS (min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (tRP) has been satisfied.
<Burst Length = 4, CAS Latency = 2 & 2.5>
01
23
4
5
67
8
9
COM M A N D
Bank A
ACTIVE
NO P
NOP
NOP
NO P
NOP
NOP
NOP
Read A
Auto Precharge
CLK
CLK
DQS
DQ's
CAS Latency = 2
CAS Latency = 2.5
DOUT 0
t RP
NO P
* Bank can be reactivated at
completion of precharge
Auto-Precharge starts
Hi -Z
Hi - Z
t RA S ( m i n )
DOUT 1 DOUT 2 DOUT 3
DQS
DQ's
DOUT 0
Hi - Z
Hi - Z
DOUT 1 DOUT 2 DOUT 3
When the Read with Auto Precharge command is issued, new command can be asserted at 4, 5 and 6 respectively as follow.
For the same bank
For the different bank
Asserted
Command
4
5
6
4
5
6
READ
READ
Illegal
Illegal
Legal
Legal
Legal
READ with AP
*1
READ with AP
Illegal
Illegal
Legal
Legal
Legal
Active
Illegal
Illegal
Illegal
Legal
Legal
Legal
Precharge
Legal
Legal
Illegal
Legal
Legal
Legal
Note 1: AP = Auto Precharge


Similar Part No. - M13L2561616A-2A

ManufacturerPart #DatasheetDescription
logo
Elite Semiconductor Mem...		 M13L32321A-2G ESMT-M13L32321A-2G Datasheet
1Mb / 48P		    Double-data-rate architecture, two data transfers per clock cycle
More results

Similar Description - M13L2561616A-2A

ManufacturerPart #DatasheetDescription
logo
Elite Semiconductor Mem...		 M13S128324A-2M ESMT-M13S128324A-2M Datasheet
1Mb / 48P		    Double-data-rate architecture, two data transfers per clock cycle
M13S5121632A-2S ESMT-M13S5121632A-2S Datasheet
705Kb / 48P		    Double-data-rate architecture, two data transfers per clock cycle
M13S2561616A-2S ESMT-M13S2561616A-2S Datasheet
1Mb / 49P		    Double-data-rate architecture, two data transfers per clock cycle
logo
Winbond		 W9412G2IB4 WINBOND-W9412G2IB4 Datasheet
832Kb / 50P		    Double Data Rate architecture; two data transfers per clock cycle
W9412G6JH-5 WINBOND-W9412G6JH-5 Datasheet
1Mb / 53P		    Double Data Rate architecture; two data transfers per clock cycle
logo
Elite Semiconductor Mem...		 M13S2561616A-2A ESMT-M13S2561616A-2A Datasheet
1Mb / 49P		    Double-data-rate architecture, two data transfers per clock cycle
logo
Winbond		 W9751G6KB-25 WINBOND-W9751G6KB-25 Datasheet
1Mb / 87P		    Double Data Rate architecture: two data transfers per clock cycle
logo
Elite Semiconductor Mem...		 M13L32321A-2G ESMT-M13L32321A-2G Datasheet
1Mb / 48P		    Double-data-rate architecture, two data transfers per clock cycle
logo
Winbond		 W631GG6KB-15 WINBOND-W631GG6KB-15 Datasheet
3Mb / 158P		    Double Data Rate architecture: two data transfers per clock cycle
W972GG6JB-25 WINBOND-W972GG6JB-25 Datasheet
1Mb / 87P		    Double Data Rate architecture: two data transfers per clock cycle
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com