M13L2561616A-2A datasheet(15/49 Pages) ESMT

Part #	M13L2561616A-2A

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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15 / 49 page

ESMT

M13L2561616A (2A)

Elite Semiconductor Memory Technology Inc.

Publication Date : Sep. 2012

Revision : 1.0

15/49

Extended Mode Register Set (EMRS)

The extended mode register stores the data enabling or disabling DLL, and selecting output drive strength. The default value of

the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or

disabling DLL. The extended mode register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR

SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of

address pins A0~A12 and BA0~BA1 in the same cycle as CS , RAS , CAS and WE going low is written in the extended

mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents

can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle

state. A0 is used for DLL enable or disable. A1 and A6 are used for selecting output drive strength. “High” on BA0 is used for

EMRS. All the other address pins except A0~A1, A6 and BA0 must be set to low for proper EMRS operation. Refer to the table

for specific codes.

BA1 BA0 A12 A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Address Bus

0

1

RFU

DS

RFU

DS DLL

Extended Mode Register

A6

A1

Drive Strength

A0

DLL Enable

0

100 % Strength

0

Enable

0

1

60 % Strength

1

Disable

1

0

RFU

1

30 % Strength

BA1

BA0

Operating Mode

0

MRS Cycle

0

1

EMRS Cycle

Note: RFU (Reserved for future use) must stay “0” during EMRS cycle.

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