M13L2561616A-2A datasheet(11/49 Pages) ESMT

Part #	M13L2561616A-2A

Description	Double-data-rate architecture, two data transfers per clock cycle

Download	49 Pages

Scroll/Zoom	100%

Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

Logo

11 / 49 page

ESMT

M13L2561616A (2A)

Elite Semiconductor Memory Technology Inc.

Publication Date : Sep. 2012

Revision : 1.0

11/49

4.

AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still

referenced to VREF (or to the crossing point for CLK/ CLK ), and parameter specifications are guaranteed for the

specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the

range between VIL(AC) and VIH(AC).

5.

Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤

0.2VDDQ is recognized as LOW.

6.

Enables on-chip refresh and address counters.

7.

IDD specifications are tested after the device is properly initialized.

8.

The CLK/ CLK input reference level (for timing referenced to CLK/ CLK ) is the point at which CLK and CLK cross;

the input reference level for signals other than CLK/ CLK , is VREF.

9.

The output timing reference voltage level is VTT.

10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not

referenced to a specific voltage level but specify when the device output is no longer driving (tHZ), or begins driving

(tLZ).

11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this

parameter, but system performance (bus turnaround) will degrade accordingly.

12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this

CLK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device.

When no writes were previously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a

previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending

on tDQSS.

13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

14. For command/address input slew rate ≥ 1.0 V/ns

15. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns

16. For CLK & CLK slew rate ≥ 1.0 V/ns

17. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be

guaranteed by device design or tester correlation.

18. Slew Rate is measured between VOH(AC) and VOL(AC).

19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device

(i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are =

50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to

crosstalk (tJIT(crosstalk)) into the clock traces.

20. tQH = tHP - tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts

for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition

followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew

and output pattern effects, and p-channel to n-channel variation of the output drivers.

21. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers

for any given cycle.

22. For each of the terms above, if not already an integer, round to the next highest integer.

Similar Part No. - M13L2561616A-2A

Manufacturer	Part #	Datasheet	Description
Elite Semiconductor Mem...	M13L32321A-2G	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle

More results

Similar Description - M13L2561616A-2A

Manufacturer	Part #	Datasheet	Description
Elite Semiconductor Mem...	M13S128324A-2M	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S5121632A-2S	705Kb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S2561616A-2S	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9412G2IB4	832Kb / 50P	Double Data Rate architecture; two data transfers per clock cycle
Winbond	W9412G6JH-5	1Mb / 53P	Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Mem...	M13S2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9751G6KB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L32321A-2G	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W631GG6KB-15	3Mb / 158P	Double Data Rate architecture: two data transfers per clock cycle
Winbond	W972GG6JB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle

More results

M13L2561616A-2A Datasheet(PDF) 11 Page - Elite Semiconductor Memory Technology Inc.

M13L2561616A-2A Datasheet(HTML) 11 Page - Elite Semiconductor Memory Technology Inc.

Similar Part No. - M13L2561616A-2A

Similar Description - M13L2561616A-2A

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL