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M13L2561616A-2A Datasheet(PDF) 10 Page - Elite Semiconductor Memory Technology Inc. |
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M13L2561616A-2A Datasheet(HTML) 10 Page - Elite Semiconductor Memory Technology Inc. |
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10 / 49 page  ESMT M13L2561616A (2A) Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2012 Revision : 1.0 10/49 AC Timing Parameter & Specifications – continued -4 -5 -6 Parameter Symbol min max min max min max Unit Note Active to Precharge command tRAS 36 70K 40 70K 42 70K ns Active to Active / Auto Refresh command period tRC 52 55 60 ns Auto Refresh to Active / Auto Refresh command period tRFC 60 70 72 ns Active to Read, Write delay tRCD 15 15 18 ns Precharge command period tRP 15 15 18 ns Active to Read with Auto Precharge command tRAP 15 15 18 ns Active bank A to Active bank B command tRRD 8 10 12 ns Write recovery time tWR 15 15 15 ns Write data in to Read command delay tWTR 2 2 2 tCK Average periodic refresh interval tREFI 7.8 7.8 7.8 us 13 Write preamble tWPRE 0.25 0.25 0.25 tCK Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 11 Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Clock to DQS write preamble setup time tWPRES 0 0 0 ns 12 Mode Register Set command cycle time tMRD 2 2 2 tCK Exit self refresh to Read command tXSRD 200 200 200 tCK Exit self refresh to non-Read command tXSNR 75 75 75 ns Auto Precharge write recovery+precharge time tDAL (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) tCK 22 Notes: 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). |
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