M13L2561616A-2A datasheet(1/49 Pages) ESMT

Part #	M13L2561616A-2A

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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ESMT

M13L2561616A (2A)

Elite Semiconductor Memory Technology Inc.

Publication Date : Sep. 2012

Revision : 1.0

1/49

DDR SDRAM

4M x 16 Bit x 4 Banks

Double Data Rate SDRAM

Features

Double-data-rate architecture, two data transfers per clock cycle

Bi-directional data strobe (DQS)

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Four bank operation

CAS Latency : 2, 2.5, 3, 4

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock (CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for READs; center-aligned with data for WRITEs

Data mask (DM) for write masking only

VDD = 3.3V ± 0.3V, VDDQ = 3.3V ± 0.3V

7.8us refresh interval

Auto & Self refresh

Ordering Information

Product ID

Max Freq.

Package

Comments

M13L2561616A -4TG2A

250MHz (DDR500)

M13L2561616A -5TG2A

200MHz (DDR400)

M13L2561616A -6TG2A

166MHz (DDR333)

66 pin TSOPII

M13L2561616A -4BG2A

250MHz (DDR500)

M13L2561616A -5BG2A

200MHz (DDR400)

M13L2561616A -6BG2A

166MHz (DDR333)

60 Ball BGA

Pb-free

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