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M13L32321A-2G Datasheet(PDF) 28 Page - Elite Semiconductor Memory Technology Inc. |
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M13L32321A-2G Datasheet(HTML) 28 Page - Elite Semiconductor Memory Technology Inc. |
28 / 48 page ESMT M13L32321A (2G) Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2012 Revision : 1.0 28/48 Power down Power down is entered when CKE is registered Low (no accesses can be in progress). If power down occurs when all banks are idle, this mode is referred to as precharge power-down; if power down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power down deactivates the input and output buffers, excluding CLK, CLK and CKE. In power down mode, CKE Low must be maintained, and all other input signals are “Don’t Care”. The minimum power down duration is at least 1 tCK + tIS. However, power down duration is limited by the refresh requirements of the device. The power down state is synchronously exited when CKE is registered High (along with a NOP or DESELECT command). A valid command may be applied 1 tCK + tIS after exit from power down. CO M M A N D CK E CLK CLK Precharge Read Enter Prec h arge pow er- do wn m ode tIS tIS tIS tIS Active E xi t P r ec har g e power-d own mo de Enter Acti ve powe r- d own m ode Exit Activ e power -d own mo de tRP Functional Truth Table Truth Table – CKE [Note 1~4, 6] CKE n-1 CKE n Current State COMMAND n ACTION n NOTE L L Power Down X Maintain Power Down L L Self Refresh X Maintain Self Refresh 7 L H Power Down NOP or DESELECT Exit Power Down L H Self Refresh NOP or DESELECT Exit Self Refresh 5, 7 H L All Banks Idle NOP or DESELECT Precharge Power Down Entry H L Bank(s) Active NOP or DESELECT Active Power Down Entry H L All Banks Idle AUTO REFRESH Self Refresh Entry H H See the Truth Tables as follow Notes: 1. CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge. 2. Current state is the state of DDR SDRAM immediately prior to clock edge n. 3. COMMAND n is the command registered at clock edge n, and ACTION n is the result of COMMAND n. 4. All states and sequences not shown are illegal or reserved. 5. DESELECT and NOP DESELECT or NOP commands should be issued on any clock edges occurring during the tXSNR or tXSRD period. A minimum of 200 clock cycles is needed before applying any executable command, for the DLL to lock. 6. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 7. VREF must be maintained during Self Refresh operation. |
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