M13L32321A-2G datasheet(43/48 Pages) ESMT

Part #	M13L32321A-2G

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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43 / 48 page

ESMT

M13L32321A (2G)

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

43/48

Power up & Initialization Sequence (based on DDR400)

VDDQ

VREF

A0 - A 7 , A9

P o w e r - up:

VDD a n d

CL K s t a b l e

BA

E x t e nde d

Mo d e

Re g i s t e r

Se t

COMMAND

DM

DQ S

t MR D

20 0 c y c le s o f C L K * *

Load

Mo d e

R egi ster

Re s e t D L L

(w i t h A 8 = H )

L oad

Mo de

R egis t er

( w it h A 8=L)

VDD

A8

T = 200u s

VTT

(system*)

tVDT >=0

CLK

CKE

NOP

t CH

t CL

t CK

t IS t IH

PRE

EMRS

MRS

PRE

AR

MRS

ACT

t IH

t IS

CODE

t IH

t IS

LV C O M S L O W L E VEL

CODE

RA

t IH

t IS

CODE

RA

t IH

t IS

t IH t IS

H i gh- Z

DQ

Hi g h - Z

t RP

t RF C

t MR D

ALL BANKS

t RF C

t IH

t IS

: D on’ t c a r e

1 1 10 1B3 2 R . A

BA

Notes:

* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.

** = tMRD is required before any command can be applied, and 200 cycles of CLK are required before an executable command

can be applied. The two Auto Refresh commands may be moved to follow the first MRS but precede the second

PRECHARGE ALL command.

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M13L32321A-2G Datasheet(PDF) 43 Page - Elite Semiconductor Memory Technology Inc.

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