M13L32321A-2G datasheet(39/48 Pages) ESMT

Part #	M13L32321A-2G

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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39 / 48 page

ESMT

M13L32321A (2G)

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

39/48

Read Interrupted by Precharge (@ BL=8)

CK E

CS

RA S

CA S

BA

WE

DQ S ( C L = 2 )

DQ ( C L = 2 )

01

234

56

789

10

HI GH

C O MMA N D

A 8 /A P

AD D R

( A 0~ A 7 , A 9)

Qa 0

Qa 1

READ

Ca

PRE

CHARGE

CL K

Qa 2

Q a 3

Qa 4

Q a 5

DM

2tCK Valid

DQ S(C L =2 . 5 )

D Q ( C L= 2 . 5)

Qa 0

Qa 1

Qa 2

Q a 3

Qa 4

Q a 5

2.5 tCK Valid

:D o n ’ t c a r e

11 1 0 1 B 3 2 R . A

When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read

burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a

new Bank Activate command may be issued to the same bank.

1.

For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the

rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate

command may be issued to the same bank after tRP (RAS Precharge time).

2.

When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge

which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data

word has been output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same bank after

tRP.

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M13L32321A-2G Datasheet(PDF) 39 Page - Elite Semiconductor Memory Technology Inc.

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