M13L32321A-2G datasheet(34/48 Pages) ESMT

Part #	M13L32321A-2G

Description	Double-data-rate architecture, two data transfers per clock cycle

Download	48 Pages

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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34 / 48 page

ESMT

M13L32321A (2G)

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

34/48

Read with Auto Precharge (@ BL=8)

CK E

CS

RA S

CA S

BA

WE

DQ S ( C L = 2 )

DQ ( C L = 2 )

01

234

5

67

8910

HI G H

DM

CO M M A ND

A 8 /AP

AD D R

(A 0 ~ A7 , A 9 )

Qa 4

Q a 5

Qa 7

Qa 6

t RP

Qa 0

Qa 1

Q a 3

Qa 2

ACTIVE

READ

Ca

A u to pr ec har g e s t ar t

Not e 1

CL K

Ra

DQ S( C L = 2 . 5 )

D Q ( C L = 2. 5)

Qa 4

Q a 5

Qa 7

Qa 6

Qa 0

Qa 1

Qa 3

Qa 2

:D o n ’ t c a r e

1 1 10 1B 3 2 R . A

Note: 1. The row active command of the precharge bank can be issued after tRP from this point.

The new read/write command of another activated bank can be issued from this point.

At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.

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M13L32321A-2G Datasheet(PDF) 34 Page - Elite Semiconductor Memory Technology Inc.

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