M13L32321A-2G datasheet(26/48 Pages) ESMT

Part #	M13L32321A-2G

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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26 / 48 page

ESMT

M13L32321A (2G)

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

26/48

Write with Auto Precharge

If A8 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the same

bank should not be issued until the internal precharge is completed. The internal precharge begins at the rising edge of the CLK with

the tWR delay after the last data-in.

01

23

4

5

6

7

8

CO M M A ND

DQ S

DQ ' s

Bank A

ACT I V E

NO P

DIN 0

Write A

Auto Precharge

*Bank can be reactivated

at completion of tRP

t WR

t RP

Inter nal pr ec har g e s t ar t

CL K

DIN 1

DIN 2 DIN 3

At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.

For the same bank

For the different bank

Asserted

Command

4

5

6

7

8

4

5

6

7

8

WRITE

Illegal

Legal

WRITE with AP

*1

WRITE

with AP

WRITE

with AP

Illegal

Legal

READ

Illegal

READ +

DM

*2

READ+

DM

READ

Illegal

Legal

READ with AP

Illegal

READ

with AP+

DM

READ

with AP+

DM

READ

with AP

Illegal

Legal

Active

Illegal

Legal

Precharge

Illegal

Legal

Note: 1. AP = Auto Precharge

2. DM: Refer to “Write Interrupted by a Read & DM“

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M13L32321A-2G Datasheet(PDF) 26 Page - Elite Semiconductor Memory Technology Inc.

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