ESMT

M13L32321A (2G)

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

23/48

Write Interrupted by a Precharge & DM

A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access

any residual data from the burst write cycle must be masked by DM.

<Burst Length = 8>

01

23

4

5

6

7

8

CO M M A N D

DQ S

DQ ' s

DQ S

DQ ' s

NO P

NO P

NOP

NO P

NOP

WRITE A

DM

CL K

CLK

DM

Precharge A

Hi - Z

Hi - Z

Hi - Z

Hi - Z

NOP

W RITE B

Precharge timing for Write operations in DRAMs requires enough time to allow “write recovery” which is the time required by a DRAM

the required of time between the last valid write operation and a Precharge command to the same bank.

strobes in the precharge command.

1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write

2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time

between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input

Activate commands. During write with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest

possible external Precharge command without interrupting the Write burst as described in 1 above.

command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt

the burst.

5. Refer to “Burst write operation”