ESMT

M13L32321A (2G)

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

22/48

Write Interrupted by a Read & DM

A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock

cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any

avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be

written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command.

<Burst Length = 8, CAS Latency = 3>

01

23

4

5

678

CO M M A N D

DQ S

DQ ' s

DQ S

DQ ' s

NO P

NO P

NO P

NO P

REA D

NOP

WRITE

DM

CL K

CL K

DM

NO P

NO P

Hi - Z

Hi - Z

*5

Hi - Z

Hi - Z

*5

The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the

memory.

1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the

Write to Read delay is 1 clock cycle is disallowed.

2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately precede

the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.

3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller)

in time to allow the buses to turn around before the SDRAM drives them during a read operation.

4. If input Write data is masked by the Read command, the DQS inputs are ignored by the DDR SDRAM.

5. Refer to “Burst write operation”