M13L32321A-2G datasheet(20/48 Pages) ESMT

Part #	M13L32321A-2G

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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20 / 48 page

ESMT

M13L32321A (2G)

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

20/48

Read Interrupted by a Precharge

A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to

precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.

01

23

4

5

6

7

8

CO M M A N D

DQ S

DQ ' s

RE A D

NOP

NO P

DOUT 0

Precharge

1t CK

NO P

I n t e r r u pt e d by pr e c h a r g e

CL K

DOUT 1 DOUT 2 DOUT 3 DOUT 4 DOUT 5 DOUT 6 DOUT 7

When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the

Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and

when a new Bank Activate command may be issued to the same bank.

1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the

rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank

Activate command may be issued to the same bank after tRP (RAS precharge time).

2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock

edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the

last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same

bank after tRP.

3. For a Read with auto precharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP

begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.

During Read with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest possible

external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.

4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a

Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time)

with the result rounded up to the nearest integer number of clock cycles.

In all cases, a Precharge operation cannot be initiated unless tRAS (min) [minimum Bank Activate to Precharge time] has been

satisfied. This includes Read with auto precharge commands where tRAS (min) must still be satisfied such that a Read with auto

precharge command has the same timing as a Read command followed by the earliest possible Precharge command which does

not interrupt the burst.

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