M13L32321A-2G datasheet(1/48 Pages) ESMT

Part #	M13L32321A-2G

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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ESMT

M13L32321A (2G)

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

1/48

DDR SDRAM

512K x 32 Bit x 2 Banks

Double Data Rate SDRAM

Features

Double-data-rate architecture, two data transfers per clock cycle

Bi-directional data strobe (DQS)

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Two bank operation

CAS Latency : 2, 2.5, 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for READs; center-aligned with data for WRITEs

Data mask (DM) for write masking only

VDD = 3.3V ± 0.3V, VDDQ = 3.3V ± 0.3V

Auto & Self refresh

15.6us refresh interval

Ordering Information

Product ID

Max Freq.

Package

Comments

M13L32321A -5BG2G

200MHz (DDR400)

M13L32321A -6BG2G

166MHz (DDR333)

M13L32321A -7.5BG2G

133MHz (DDR266)

144 ball FBGA

Pb-free

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M13L32321A-2G Datasheet(PDF) 1 Page - Elite Semiconductor Memory Technology Inc.

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