M5-512SLASH192-10VI datasheet(11/47 Pages) LATTICE

Part #	M5-512/192-10VI

Description	Fifth Generation MACH Architecture

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Manufacturer	LATTICE [Lattice Semiconductor]

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MACH 5 Family

11

SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS 1

Both the 3.3-V and 5-V VCC MACH 5 devices are safe for mixed supply voltage system designs.

The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they

accept inputs from other 3.3-V devices. The 3.3-V devices will accept inputs up to 5.5 V. Both the

3.3-V and 5-V versions have the same high-speed performance and provide easy-to-use mixed-

voltage design capability.

Note:

1. Excludes original M5-128, M5-192, and M5-256 while M5-128/1, M3-192/1 and M5-256/1 are supported. Please refer to

Application Note titled “Hot Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices”.

BUS-FRIENDLY INPUTS AND I/OS

All MACH 5 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating

two inverters in series which loop back to the input. This double inversion weakly holds the input

at its last driven logic state. While it is a good design practice to tie unused pins to a known state,

the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can

cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level

“1.” For the circuit diagram, please refer to the document entitled MACH Endurance

Characteristics on the Lattice Data Book CD-ROM or Lattice web site.

POWER MANAGEMENT

There are 4 power/speed options in each MACH 5 PAL block (Table 5). The speed and power

tradeoff can be tailored for each design. The signal speed paths in the lower-power PAL blocks

will be slower than those in the higher-power PAL blocks. This feature allows speed critical paths

to run at maximum frequency while the rest of the signal paths operate in a lower-power mode.

In large designs, there may be several different speed requirements for different portions of the

design.

PROGRAMMABLE SLEW RATE

Each MACH 5 device I/O has an individually programmable output slew rate control bit. Each

output can be individually conﬁgured for the higher speed transition (3 V/ns) or for the lower

noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate

will introduce fewer reﬂections, less noise, and keep ground bounce to a minimum. For designs

with short traces or well terminated lines, the fast slew rate can be used to achieve the highest

speed. The slew rate is adjusted independent of power.

POWER-UP RESET/SET

All ﬂip-ﬂops power up to a known state for predictable system initialization. If a macrocell is

conﬁgured to SET on a signal from the control generator, then that macrocell will be SET during

device power-up. If a macrocell is conﬁgured to RESET on a signal from the control generator or

is not conﬁgured for set/reset, then that macrocell will RESET on power-up. To guarantee

Table 5. Power Levels

High Speed/High Power

100% Power

Medium High Speed/Medium High Power

67% Power

Medium Low Speed/Medium Low Power

40% Power

Low Speed/Low Power

20% Power

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M5-512/192-10VI Datasheet(PDF) 11 Page - Lattice Semiconductor

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