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LTC2755 Datasheet(PDF) 15 Page - Linear Technology |
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LTC2755 Datasheet(HTML) 15 Page - Linear Technology |
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15 / 24 page  LTC2755 15 2755f OPERATION the D/S pin. The selected I/O port’s pins become logic outputs during readback, while the unselected I/O port’s pins remain high-impedance inputs. With the DAC channel and I/O port selected, assert READ high and select the desired input or DAC register using the UPD pin. Note that UPD is a two function pin—the update function is only available when READ is low. When READ is high, the update function is disabled and the UPD pin instead selects the input or DAC register for readback. Table 1 shows the readback functions for the LTC2755. Table 1. Write, Update and Read Functions READ D/S WR UPD SPAN I/O DATA I/O 0 0 0 0 - Write to Input Register 0 0 0 1 - Write/Update (Transparent) 00 1 0 - - 0 0 1 1 Update DAC Register Update DAC Register 0 1 0 0 Write to Input Register - 0 1 0 1 Write/Update (Transparent) - 01 1 0 - - 0 1 1 1 Update DAC register Update DAC Register 1 0 X 0 - Read Input Register 1 0 X 1 - Read DAC Register 1 1 X 0 Read Input Register - 1 1 X 1 Read DAC Register - X = Don’t Care The most common readback task is to check the contents of an input register after writing to it, before updating the new data to the DAC register. To do this, hold UPD low and assert READ high. The contents of the selected port’s input register are output to its I/O pins. To read back the contents of a DAC register, hold UPD low and assert READ high, then bring UPD high to select the DAC register. The contents of the selected DAC register are output by the selected port’s I/O pins. Note: if no update is desired after the readback operation, UPD must be returned low before bringing READ low; otherwise the UPD pin will revert to its primary function and update the DAC. These devices also have a power-on reset that initializes all DACs to VOUT = 0V in any output range. The DACs power up in the 0V-5V range if the part is in SoftSpan configuration; for manual span (see Manual Span Configuration below), the DACs power up in the manually-chosen range at the appropriate code. Manual Span Configuration Multiple output ranges are not needed in some applications. To configure the LTC2755 for single-span operation, tie the MSPAN pin to VDD and the D/S pin to GND. The desired output range is then specified by the span I/O pins (S0, S1 and S2) as usual, but the pins are programmed by tying directly to GND or VDD (see Figure 1 and Table 2). In this configuration, all DAC channels will initialize to the chosen output range at power-up, with VOUT = 0V. When configured for manual span operation, span pin readback is disabled. Readback The contents of any one of the 16 interface registers can be read back from the I/O ports. The I/O pins are grouped into two ports: data and span. The data I/O port comprises pins D0-D11, D0-D13 or D0-D15 (LTC2755-12, LTC2755-14 or LTC2755-16, respectively). The span I/O port comprises pins S0, S1 and S2 for all parts. Each DAC channel has a set of data registers that are controlled and read back from the data I/O port; and a set of span registers that are controlled and read back from the span I/O port. The register structure is shown in the Block Diagram. A readback operation is initiated by asserting READ to logic high after selecting the desired DAC channel and I/O port. The I/O pins, which are high-impedance digital inputs when READ is low, selectively change to low-impedance logic outputs during readback. Select the DAC channel with address pins A0, A1 and A2, and select the I/O port (data or span) to be read back with |
Similar Part No. - LTC2755_15 |
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