18

LT1720/LT1721

Optional Logarithmic Pulse Stretcher

The fourth comparator of the quad LT1721 can be put to

work as a logarithmic pulse stretcher. This simple circuit

can help tremendously if you don’t have a fast enough

oscilloscope (or control circuit) to easily capture 3ns pulse

widths (or faster). When an input pulse occurs, C2 is

hysteresis and 10mV offset across R3 are overcome

output high. When the input pulse subsides, C2 dis-

charges with a 540ns time constant, keeping the compara-

tor on until the decay overrides the 10mV offset across R3

minus hysteresis. Because of this exponential decay, the

output pulse width will be proportional to the logarithm of

the input pulse width. It is important to bypass the circuit’s

keeps the quiescent input voltage in a range where forward

comparator is not a problem.

input pulse as:

–

(1)

where

the capture time constant

the decay time constant

the voltage drop across R1

LT1721 hysteresis

the input pulse voltage after

the diode drop

the effective source voltage

for the charge

delay in turn-on due to offset and hysteresis, the equation

can be approximated by:

(2)

For example, an 8ns input pulse gives a 1.67

µs output

pulse. Doubling the input pulse to 16ns lengthens the

output pulse by 0.37

µs. Doubling the input pulse again to

32ns adds another 0.37

µs to the output pulse, and so on.

The rate of 0.37

µs per octave falls out of the above

equation as:

(3)

There is

uncertainty referred to the input pulse of less than 2%

(60ps resolution on a 3ns pulse with a 60MHz oscillo-

scope—not bad!). The beauty of this circuit is that it gives

resolution precisely where it’s hardest to get. The jitter is

due to a combination of the slow decay of the last few

millivolts on C2 and the 4nV/

√Hz noise and 400MHz

bandwidth of the LT1721 input stage. Increasing the offset

across R3 or decreasing

expense of dynamic range.

The circuit topology itself is extremely fast, limited theo-

retically only by the speed of the diode, the capture time

constant

shows results achieved with the implementation shown,

compared to a plot of equation (1). The low end is limited

by the delivery time of the upstream comparators. As the

input pulse width is increased, the log function is con-

strained by the asymptotic RC response but, rather than

becoming clamped, becomes time linear. Thus, for very

long input pulses the third term of equation (1) dominates

and the circuit becomes a 3

µs pulse stretcher.

capacitor.

of

this effective delay will be 2ns.

Thevenin equivalent charge voltage seen by C2 is boosted slightly by R2 being terminated above

ground.