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UPD753204 Datasheet(PDF) 5 Page - NEC |
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UPD753204 Datasheet(HTML) 5 Page - NEC |
5 / 80 page ![]() 5 µPD753204, 753206, 753208 1. PIN CONFIGURATION (TOP VIEW) • 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) µPD753204GT-×××, µPD753206GT-×××, µPD753208GT-××× Note Connect IC (Internally Connected) pin directly to VDD. Pin Identification P00 to P03 : Port0 S12 to S23 : Segment Output 12 to 23 P10, P13 : Port1 VLC0 to VLC2 : LCD Power Supply 0 to 2 P20 to P23 : Port2 BIAS : LCD Power Supply Bias Control P30 to P33 : Port3 LCDCL : LCD Clock P50 to P53 : Port5 SYNC : LCD Synchronization P60 to P63 : Port6 TI0 : Timer Input 0 P80 to P83 : Port8 PTO0 to PTO2 : Programmable Timer Output 0 to 2 P90 to P93 : Port9 BUZ : Buzzer Clock KR0 to KR3 : Key Return 0 to 3 PCL : Programmable Clock COM0 to COM3 : Common Output 0 to 3 INT0, INT4 : External Vectored Interrupt 0, 4 SCK : Serial Clock X1, X2 : System Clock Oscillation 1, 2 SI : Serial Input RESET : Reset SO : Serial Output IC : Internally Connected SB0, SB1 : Serial Data Bus 0, 1 VDD : Positive Power Supply VSS : Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 P30/LCDCL P31/SYNC P32 P33 VSS P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 VDD X1 X2 S12 S13 S14 S15 P93/S16 P92/S17 P91/S18 P90/S19 P83/S20 P82/S21 P81/S22 P80/S23 P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P10/INT0 P03/SI/SB1 P02/SO/SB0 P01/SCK P00/INT4 RESET IC Note |
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