PALCE22V10 and PALCE22V10Z Families

31

POWER-UP RESET

The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been

powered up. The output state will depend on the programmed pattern. This feature is valuable in

simplifying state machine initialization. A timing diagram and parameter table are shown below.

to its steady state, two conditions are required to ensure a valid power-up reset. These conditions

are:

x

x

Following reset, the clock input must not be driven from LOW to HIGH until all applicable input

and feedback setup times are met.

Parameter

Symbol

Parameter Description

Max

Unit

Power-up Reset Time

1000

ns

Input or Feedback Setup Time

See Switching

Characteristics

Clock Width LOW

tPR

tS

4 V

VCC

Power

Registered

Active-Low

Output

Clock

Figure 3. Power-Up Reset Waveform

VCC Off

16564E-021