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PALCE22V10 Datasheet(PDF) 3 Page - Lattice Semiconductor |
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PALCE22V10 Datasheet(HTML) 3 Page - Lattice Semiconductor |
3 / 34 page ![]() PALCE22V10 and PALCE22V10Z Families 3 Variable Input/Output Pin Ratio The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to VCC or GND. Registered Output Configuration Each macrocell of the PALCE22V10 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration (S1 = 0), the array feedback is from Q of the flip-flop. Combinatorial I/O Configuration Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin. 0 = Programmed EE bit 1 = Erased (charged) EE bit Figure 1. Output Logic Macrocell Diagram 16564E-004 CLK S1 10 11 00 01 AR SP 0 1 I/On S0 D Q Q S1 S0 Output Configuration 0 0 Registered/Active Low 0 1 Registered/Active High 1 0 Combinatorial/Active Low 1 1 Combinatorial/Active High |
Similar Part No. - PALCE22V10 |
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Similar Description - PALCE22V10 |
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