PALCE22V10 and PALCE22V10Z Families

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Note that preset and reset control the flip-flop, not the output pin. The output level is determined

by the output polarity selected.

Power-Up Reset

All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the

and the reset delay time is 1000ns maximum.

Register Preload

The register on the PALCE22V10 can be preloaded from the output pins to facilitate functional

testing of complex state machine designs. This feature allows direct loading of arbitrary states,

making it unnecessary to cycle through long test vector sequences to reach a desired state. In

addition, transitions from illegal states can be verified by loading illegal states and observing

proper recovery.

Security Bit

After programming and verification, a PALCE22V10 design can be secured by programming the

security EE bit. Once programmed, this bit defeats readback of the internal programmed pattern

by a device programmer, securing proprietary designs from competitors. When the security bit is

programmed, the array will read as if every bit is erased, and preload will be disabled.

The bit can only be erased in conjunction with erasure of the entire pattern.

Programming and Erasing

The PALCE22V10 can be programmed on standard logic programmers. It also may be erased to

reset a previously configured device back to its unprogrammed state. Erasure is automatically

performed by the programming hardware. No special erase operation is required.

Quality and Testability

The PALCE22V10 offers a very high level of built-in quality. The erasability of the device provides

a direct means of verifying performance of all AC and DC parameters. In addition, this verifies

complete programmability and functionality of the device to provide the highest programming

yields and post-programming functional yields in the industry.

Technology

The high-speed PALCE22V10 is fabricated with Vantis’ advanced electrically erasable (EE) CMOS

process. The array connections are formed with proven EE cells. Inputs and outputs are designed

to be compatible with TTL devices. This technology provides strong input clamp diodes, output

slew-rate control, and a grounded substrate for clean switching.

PCI Compliance

The PALCE22V10H devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local

Bus Specification published by the PCI Special Interest Group. The PALCE22V10H’s predictable

timing ensures compliance with the PCI AC specifications independent of the design.

Zero-Standby Power Mode

The PALCE22V10Z features a zero-standby power mode. When none of the inputs switch for an

extended period (typically 50 ns), the PALCE22V10Z will go into standby mode, shutting down