PALCE22V10 datasheet(4/34 Pages) LATTICE

Part #	PALCE22V10

Description	24-Pin EE CMOS (Zero Power) Versatile PAL Device

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Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

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PALCE22V10 and PALCE22V10Z Families

Programmable Three-State Outputs

Each output has a three-state output buffer with three-state control. A product term controls the

buffer, allowing enable and disable to be a function of any product of device inputs or output

feedback. The combinatorial output provides a bi-directional I/O pin, and may be conﬁgured as

a dedicated input if the buffer is always disabled.

Programmable Output Polarity

The polarity of each macrocell output can be active high or active low, either to match output

signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be

written in their most compact form (true or inverted), and the output can still be of the desired

polarity. It can also save “DeMorganizing” efforts.

Selection is controlled by programmable bit S0 in the output macrocell, and affects both registered

and combinatorial outputs. Selection is automatic, based on the design speciﬁcation and pin

deﬁnitions. If the pin deﬁnition and output equation have the same polarity, the output is

programmed to be active high (S0 = 1).

Preset/Reset

For initialization, the PALCE22V10 has preset and reset product terms. These terms are connected

to all registered outputs. When the synchronous preset (SP) product term is asserted high, the

output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the

asynchronous reset (AR) product term is asserted high, the output registers will be immediately

loaded with a LOW independent of the clock.

Figure 2. Macrocell Conﬁguration Options

DQ

CLK

SP

AR

a. Registered/active low

S0 = 0

S1 = 0

b. Combinatorial/active low

S0 = 0

S1 = 1

DQ

CLK

SP

AR

c. Registered/active high

S0 = 1

S1 = 0

d. Combinatorial/active high

S0 = 1

S1 = 1

16564E-005

Q

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