Specifications ispLSI 2128E

7

ispLSI 2128E Timing Model

Note: Calculations are based upon timing specifications for the ispLSI 2128E-180L.

Derivations of

=

=

=

=

Logic + Reg su - Clock (min)

(

(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)

(0.5 + 0.6 + 3.9) + (0.7) - (0.5 + 0.6 + 1.0)

=

=

=

=

Clock (max) + Reg h - Logic

(

(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)

(0.5 + 0.6 + 4.0) + (3.3) - (0.5 + 0.6 + 3.9)

=

=

=

=

Clock (max) + Reg co + Output

(

(#20 + #22 + #35) + (#31) + (#36 + #38)

(0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 0.6)

Table 2-0042/2128E

7.9

3.4

3.6

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

Reg 4 PT Bypass

20 PT

XOR Delays

Control

PTs

I/O Pin

(Input)

Y0,1,2

GRP

GLB Reg Bypass

ORP Bypass

DQ

RST

RE

OE

CK

I/O Delay

I/O Cell

ORP

GLB

GRP

I/O Cell

#24

#25 - 27

#33 - 35

#43, 44

#36

Reset

Ded. In

#21

#20

#28

#29 - 32

GOE0, 1

#42

#40, 41

0491/2128E

#22

Comb 4 PT Bypass #23

#37

#45

#38,

#39