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M37225M6 Datasheet(PDF) 27 Page - Renesas Technology Corp |
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M37225M6 Datasheet(HTML) 27 Page - Renesas Technology Corp |
27 / 128 page M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 25 of 124 REJ03B0136-0100Z Fig. 8.4.2 Timer Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) [Address 00F516] B After reset RW Timer Mode Register 2 0 Name Functions Timer 3 count source selection bit (TM20) 0 RW 1 Timer 4 internal interrupt count source selection bit (TM21) 0 RW 2 3 Timer 3 count stop bit (TM22) 0: Count start 1: Count stop Timer 4 count stop bit (TM23) 0: Count start 1: Count stop 0 0 4 Timer 4 count source selection bit (TM24) 0: Internal clock source 1: f(XIN)/2 0 5 Timer 3 external count source selection bit (TM25) 0: TIM3 pin input 1: HSYNC pin input 0 RW RW RW RW 0 : f(XIN)/16 1 : External clock source 0 : Timer 3 overflow signal 1 : f(XIN)/16 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0— R Fig. 8.4.1 Timer Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) [Address 00F416] B After reset W Timer Mode Register 1 0 1 2 3 4 Name Functions Timer 1 count source selection bit 1 (TM10) 0: f(XIN)/16 1: f(XIN)/4096 Timer 2 count source selection bit 1 (TM11) 0: Interrupt clock source 1: External clock from TIM2 pin Timer 1 count stop bit (TM12) 0: Count start 1: Count stop Timer 2 count stop bit (TM13) 0: Count start 1: Count stop Timer 2 internal count source selection bit 2 (TM14) R 0 0 0 0 0 W R W R W R W R W R 0: f(XIN)/16 1: Timer 1 overflow 5 <At execution of STP instruction> Timers 3 and 4 auto set disable bit (TM15) 0: Auto set enabled 1: Auto set disabled 0 W R 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0— R |
Similar Part No. - M37225M6_15 |
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Similar Description - M37225M6_15 |
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