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M37225M6 Datasheet(PDF) 88 Page - Renesas Technology Corp |
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M37225M6 Datasheet(HTML) 88 Page - Renesas Technology Corp |
88 / 128 page M37225M6/M8/MA/MC-XXXSP, M37225ECSP Rev.1.00 Nov 01, 2000 page 86 of 124 REJ03B0136-0100Z 8.12. RESET CIRCUIT When the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 V ± 10 %, hold the RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as shown in Figure 8.12.2, reset is released and the program starts form the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are shown in Figures 8.2.3 to 8.2.6. An example of the reset circuit is shown in Figure 8.12.1. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V. Fig.8.12.2 Reset Sequence Fig.8.12.1 Example of Reset Circuit Power source voltage 0 V Reset input voltage 0 V 4.5 V 0.9 V Poweron Vcc RESET Vss Microcomputer 1 5 4 3 0.1 µF M51953AL XIN φ RESET Internal RESET SYNC Address Data 32768 count of X IN clock cycle (See note 3) Reset address from the vector table ? ? 01, S 01, S-1 01, S-2 FFFE FFFF ADH, ADL ? ? ? ? ? ADL ADH Notes 1 : f(XIN) and f( φ) are in the relation : f(XIN) = 2·f (φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, “FF 16” is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal. |
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Similar Description - M37225M6_15 |
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