M37225M6_15 datasheet(53/128 Pages) RENESAS

Part #	M37225M6

Description	SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

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Manufacturer	RENESAS [Renesas Technology Corp]

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M37225M6/M8/MA/MC-XXXSP, M37225ECSP

Rev.1.00

Nov 01, 2000

page 51 of 124

REJ03B0136-0100Z

Note: VREF indicates the reference voltage (= Vcc).

Fig. 8.8.3 Changes in A-D Conversion Register and Comparison Voltage during A-D Conversion

8.8.6 Conversion Method

➀ Set the A-D conversion interrupt request bit to “0” (even when A-

D conversion is started, the A-D conversion interrupt reguest bit

is not set to “0” automatically).

➁ When using A-D conversion interrupt, enable interrupts by setting

A-D conversion interrupt enable bit to “1” and setting the interrupt

disable flag to “0.”

➂ Set the VCC connection selection bit to “1” to connect VCC to the

resistor ladder.

➃ Select analog input pins by the analog input selection bit of the

A-D control register.

➄ Set the A-D conversion completion bit to “0.” This write operation

starts the A-D conversion. Do not read the A-D conversion regis-

ter during the A-D conversion.

➅ Verify the completion of the conversion by the state (“1”) of the

A-D conversion completion bit, the state (“1”) of A-D conversion

interrupt reguest bit, or the occurrence of an A-D conversion in-

terrupt.

➆ Read the A-D conversion register to obtain the conversion re-

sults.

Note : When the ladder resistor is disconnect from VCC, set the VCC connec-

tion selection bit to “0” between steps ➅ and ➆.

8.8.7 Internal Operation

When the A-D conversion starts, the following operations are auto-

matically performed.

➀ The A-D conversion register is set to “0016.”

➁ The most significant bit of the A-D conversion register becomes

“1, ” and the comparison voltage “Vref” is input to the comparator.

At this point, Vref is compared with the analog input voltage “VIN .”

➂ Bit 7 is determined by the comparison results as follows.

When Vref < VIN : bit 7 holds “1”

When Vref > VIN : bit 7 becomes “0”

With the above operations, the analog value is converted into a digi-

tal value. The A-D conversion terminates in a maximum of 50 ma-

chine cycles (8.5

µs at f(XIN) = 8 MHz) after it starts, and the conver-

sion result is stored in the A-D conversion register.

An A-D conversion interrupt request occurs at the same time as A-D

conversion completion, the A-D conversion interrupt request bit be-

comes “1.” The A-D conversion completion bit also becomes “1.”

Table 8.8.1 Expression for Vref and VREF

A-D conversion register contents “n”

(decimal notation)

0

1 to 255

Vref (V)

0

VREF

2

VREF

512

VREF

2

VREF

4

VREF

512

VREF

2

VREF

4

VREF

8

VREF

512

VREF

2

VREF

4

VREF

8

VREF

512

VREF

256

12 3 456 7 8

1 0000 0 0 0

12

100

0 0

0

1000

0 0

0

1

12 3 4 5 6

7 1

–

±

–

±±

0 000 0

0 0 0

Contents of A-D conversion register

Reference voltage (Vref)

[V]

0

A-D conversion start

1st comparison start

3rd comparison start

8th comparison start

2nd comparison start

Digital value corresponding to

analog input voltage.

A-D conversion completion

(8th comparison completion)

±±

±

–

±

.......

: Value determined by mth (m = 1 to 8) result

m

.....

VREF

256

✕ (n – 0.5)

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