M37225M6_15 datasheet(44/128 Pages) RENESAS

Part #	M37225M6

Description	SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

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Manufacturer	RENESAS [Renesas Technology Corp]

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M37225M6/M8/MA/MC-XXXSP, M37225ECSP

Rev.1.00

Nov 01, 2000

page 42 of 124

REJ03B0136-0100Z

Fig. 8.6.12 Address Data Communication Format

S

Slave address

A

Data

A

Data

A/A

P

R/W

7 bits

“0”

1 to 8 bits

S

Slave address

A

Data

A

Data

AP

7 bits

“1”

1 to 8 bits

(1) A master-transmitter transmits data to a slave-receiver

S

Slave address

1st 7 bits

A

Data

7 bits

“0”

8 bits

1 to 8 bits

(2) A master-receiver receives data from a slave-transmitter

Slave address

2nd byte

A

Data

A/A

P

1 to 8 bits

S

Slave address

1st 7 bits

A

7 bits

“0”

8 bits

7 bits

(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address

Slave address

2nd byte

Data

1 to 8 bits

Sr

Slave address

1st 7 bits

A

Data

A

P

1 to 8 bits

“1”

(4) A master-receiver receives data from a slave-transmitter with a 10-bit address

S : START condition

P : STOP condition

A : ACK bit

R/W : Read/Write bit

Sr : Restart condition

From master to slave

From slave to master

R/W

8.6.12 Precautions when using multi-master

I2C-BUS interface

(1) Read-modify-write instruction

The precautions when the raead-modify-write instruction such as SEB,

CLB etc. is executed for each register of the multi-master I2C-BUS

interface are described below.

•I2C data shift register (S0)

When executing the read-modify-write instruction for this register

during transfer, data may become a value not intended.

•I2C address register (S0D)

When the read-modify-write instruction is executed for this register

at detecting the STOP condition, data may become a value not

______

intended. It is because hardware changes the read/write bit (RBW)

at the above timing.

•I2C status register (S1)

Do not execute the read-modify-write instruction for this register

because all bits of this register are changed by hardware.

•I2C control register (S1D)

When the read-modify-write instruction is executed for this register

at detecting the START condition or at completing the byte transfer,

data may become a value not intended. Because hardware changes

the bit counter (BC0–BC2) at the above timing.

•I2C clock control register (S2)

The read-modify-write instruction can be executed for this register.

(2) START condition generating procedure us-

ing multi-master

➀Procedure example (The necessary conditions of the generating

procedure are described as the following ➁ to ➄).

•

LDA

—

(Taking out of slave address value)

SEI

(Interrupt disabled)

BBS 5,S1,BUSBUSY

(BB flag confirming and branch process)

BUSFREE:

STA S0

(Writing of slave address value)

LDM #$F0, S1

(Trigger of START condition generating)

CLI

(Interrupt enabled)

•

BUSBUSY:

CLI

(Interrupt enabled)

•

➁Use “STA,” “STX” or “STY” of the zero page addressing instruction

for writing the slave address value to the I2C data shift register.

➂Use “LDM” instruction for setting trigger of START condition gener-

ating.

➃Write the slave address value of above ➁ and set trigger of START

condition generating of above ➂ continuously shown the above

procedure example.

➄Disable interrupts during the following three process steps:

• BB flag confirming

• Writing of slave address value

• Trigger of START condition generating

When the condition of the BB flag is bus busy, enable interrupts

immediately.

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