M37225M6_15 datasheet(42/128 Pages) RENESAS

Part #	M37225M6

Description	SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

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Manufacturer	RENESAS [Renesas Technology Corp]

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M37225M6/M8/MA/MC-XXXSP, M37225ECSP

Rev.1.00

Nov 01, 2000

page 40 of 124

REJ03B0136-0100Z

8.6.8 START/STOP Condition Detect Conditions

The START/STOP condition detect conditions are shown in

Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table

8.6.3 are satisfied, a START/STOP condition can be detected.

Note: When a STOP condition is detected in t he slave mode

(MST = 0), an interrupt request signal “IICIRQ” is generated to the

CPU.

Fig. 8.6.11 START Condition/STOP Condition Detect Timing Dia-

gram

Standard Clock Mode

6.5

µs (26 cycles) < SCL

release time

3.25

µs (13 cycles) < Setup time

3.25

µs (13 cycles) < Hold time

High-speed Clock Mode

1.0

µs (4 cycles) < SCL

release time

0.5

µs (2 cycles) < Setup time

0.5

µs (2 cycles) < Hold time

Table 8.6.3 START Condition/STOP Condition Detect Conditions

Note: Absolute time at

φ = 4 MHz. The value in parentheses denotes the num-

ber of

φ cycles.

Hold time

Setup

time

SCL

SDA

(START condition)

SDA

(STOP condition)

SCL release time

Hold time

Setup

time

8.6.9 Address Data Communication

There are two address data communication formats, namely, 7-bit

addressing format and 10-bit addressing format. The respective ad-

dress communication formats is described below.

(1) 7-bit addressing format

To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C

control register (address 00DA16) to “0.” The first 7-bit address data

transmitted from the master is compared with the high-order 7-bit

slave address stored in the I2C address register (address 00D816).

At the time of this comparison, address comparison of the RBW bit of

the I2C address register (address 00D816) is not made. For the data

transmission format when the 7-bit addressing format is selected,

refer to Figure 8.6.12, (1) and (2).

(2) 10-bit addressing format

To meet the 10-bit addressing format, set the 10BIT SAD bit of the

I2C control register (address 00DA16) to “1.” An address comparison

is made between the first-byte address data transmitted from the

master and the 7-bit slave address stored in the I2C address register

(address 00D816). At the time of this comparison, an address com-

parison between the RBW bit of the I2C address register (address

00D816) and the R/W bit which is the last bit of the address data

transmitted from the master is made. In the 10-bit addressing mode,

the R/W bit which is the last bit of the address data not only specifies

the direction of communication for control data but also is processed

as an address data bit.

When the first-byte address data matches the slave address, the

AAS bit of the I2C status register (address 00D916) is set to “1.” After

the second-byte address data is stored into the I2C data shift register

(address 00D716), make an address comparison between the sec-

ond-byte data and the slave address by software. When the address

data of the 2nd bytes matches the slave address, set the RBW bit of

the I2C address register (address 00D816) to “1” by software. This

processing can match the 7-bit slave address and R/W data, which

are received after a RESTART condition is detected, with the value

of the I2C address register (address 00D816). For the data transmis-

sion format when the 10-bit addressing format is selected, refer to

Figure 8.6.12, (3) and (4).

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