M37225M6_15 datasheet(34/128 Pages) RENESAS

Part #	M37225M6

Description	SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

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Manufacturer	RENESAS [Renesas Technology Corp]

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M37225M6/M8/MA/MC-XXXSP, M37225ECSP

Rev.1.00

Nov 01, 2000

page 32 of 124

REJ03B0136-0100Z

8.6.1 I2C Data Shift Register

The I2C data shift register (S0 : address 00D716) is an 8-bit shift

register to store receive data and write transmit data.

When transmit data is written into this register, it is transferred to the

outside from bit 7 in synchronization with the SCL clock, and each

time one-bit data is output, the data of this register are shifted one bit

to the left. When data is received, it is input to this register from bit 0

in synchronization with the SCL clock, and each time one-bit data is

input, the data of this register are shifted one bit to the left.

The I2C data shift register is in a write enable status only when the

ESO bit of the I2C control register (address 00DA16) is “1.” The bit

counter is reset by a write instruction to the I2C data shift register.

When both the ESO bit and the MST bit of the I2C status register

(address 00D916) are “1,” the SCL is output by a write instruction to

the I2C data shift register. Reading data from the I2C data shift regis-

ter is always enabled regardless of the ESO bit value.

Note: To write data into the I2C data shift register after setting the MST bit to

“0” (slave mode), keep an interval of 8 machine cycles or more.

Fig. 8.6.2 Data Shift Register

b7 b6 b5 b4 b3 b2 b1 b0

0

Read/write bit

(RBW)

1

to

7

Slave address

(SAD0 to SAD6)

The last significant bit of address data is

compared.

0: Wait the first byte of slave address after

START condition

(read state)

1: Wait the first byte of slave address after

RESTART condition

(write state)

0

The address data is compared.

I2C Address Register

I2C address register (S0D) [Address 00D816]

B

Name

Functions

After reset R W

R—

R W

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