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UPD178004A Datasheet(PDF) 16 Page - NEC |
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UPD178004A Datasheet(HTML) 16 Page - NEC |
16 / 56 page 16 µPD178004A, 178006A, 178016A, 178018A 5.2 CLOCK GENERATOR The instruction execution time can be changed as follows. 0.44 µs/0.88 µs/1.78 µs/3.56 µs/7.11 µs/14.22 µs (@ 4.5-MHz crystal oscillator with system clock.) Figure 5-1. Clock Generator Block Diagram X1 X2 fXX Prescaler System Clock Oscillator Clock to peripheral hardware other than the above. Clock to the PLL frequency synthesizer, basic timer and buzzer output control circuit. CPU Clock (fCPU) Standby Control Circuit Wait Control Circuit To INTP0 Sampling Clock 2 fXX 22 fXX 23 fXX 24 fXX Prescaler Selector Selector fX fX 2 STOP Scaler 5.3 TIMER The µPD178004A, 178006A, 178016A, and 178018A incorporate 5 channels of the timer. • Basic timer : 1 channel • 8-bit timer/event counter : 2 channels • 8-bit timer (D/A converter) Note : 1 channel • Watchdog timer : 1 channel Note Used is shared with the 8/9-bit resolution × 3-channel D/A converter (PWM output). Figure 5-2. Basic Timer Block Diagram Divider 4.5 MHz INTTMC |
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Similar Description - UPD178004A |
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