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UPD178004A Datasheet(PDF) 4 Page - NEC |
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UPD178004A Datasheet(HTML) 4 Page - NEC |
4 / 56 page µPD178004A, 178006A, 178016A, 178018A 4 Product name µPD178004A µPD178006A µPD178016A µPD178018A Item PLL frequency Division mode Two types synthesizer • Direct division mode (VCOL pin) • Pulse swallow mode (VCOH and VCOL pins) Reference frequency 7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz) Charge pump Error out output: 2 (EO0 and EO1 pins Note 1) Phase comparator Unlock detectable by program Frequency counter • Frequency measurement • AMIFC pin: for 450-kHz count • FMIFC pin: for 450-kHz/10.7-MHz count D/A converter (PWM output) 8-/9-bit resolution × 3 channels (shared by 8-bit timer) Standby function • HALT mode • STOP mode Reset • Reset by RESET pin • Internal reset by watchdog timer • Reset by power-ON clear circuit (3-value detection) • Detection of less than 4.5 V Note 2 (CPU clock: fX) • Detection of less than 3.5 V Note 2 (CPU clock: fX/2 or less and on power application) • Detection of less than 2.5 V Note 2 (in STOP mode) Power supply voltage • VDD = 4.5 to 5.5 V (with PLL operating) •VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less) •VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX) Package • 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch) Notes 1. The EO1 pin can be set to high impedance for the µPD178016A and 178018A. The following shows an application example. PD178016A PD178018A µ µ EO0 EO1 VCOH VCOL LPF VCO To Mixer LPF : Low path filter VCO : Voltage controlled oscillator • To lock to a target frequency at high speed Setting the EO0 and EO1 pins to error out output improves the output current potential and LPF voltage control potential. • Normal state Setting only the EO0 pin to error out output maintains the LPF stable. 2. These voltage values are maximum values. Reset is actually executed at a voltage lower than these values. (2/2) |
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