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UPD178004A Datasheet(PDF) 39 Page - NEC |
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UPD178004A Datasheet(HTML) 39 Page - NEC |
39 / 56 page ![]() 39 µPD178004A, 178006A, 178016A, 178018A (b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1 ... internal clock output) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit SCK1 cycle time tKCY9 4.5 V ≤ VDD ≤ 5.5 V 800 ns 3.5 V ≤ VDD < 4.5 V 1 600 ns SCK1 high/low-level width tKH9, 4.5 V ≤ VDD ≤ 5.5 V tKCY9/2 – 50 ns tKL9 3.5 V ≤ VDD < 4.5 V tKCY9/2 – 100 ns SI1 setup time (to SCK1 ↑)tSIK9 4.5 V ≤ VDD ≤ 5.5 V 100 ns 3.5 V ≤ VDD < 4.5 V 150 ns SI1 hold time (from SCK1 ↑)tKSI9 400 ns SO1 output delay time (from SCK1 ↓) tKSO9 C = 100 pF Note 300 ns Parameter Symbol Test Conditions MIN. TYP. MAX. Unit SCK1 cycle time tKCY10 4.5 V ≤ VDD ≤ 5.5 V 800 ns 3.5 V ≤ VDD < 4.5 V 1 600 ns SCK1 high/low-level width tKH10, 4.5 V ≤ VDD ≤ 5.5 V 400 ns tKL10 3.5 V ≤ VDD < 4.5 V 800 ns SI1 setup time (to SCK1 ↑)tSIK10 100 ns SI1 hold time (from SCK1 ↑)tKSI10 400 ns SO1 output delay time (from SCK1 ↓)tKSO10 C = 100 pF Note 300 ns SCK1 at rising or falling edge time tR10, tF10 1 000 ns Note C is the load capacitance of SO1 output line. (ii) 3-wire serial I/O mode (SCK1 ... external clock input) Note C is the load capacitance of SO1 output line. |
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