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UPD178004A Datasheet(PDF) 38 Page - NEC |
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UPD178004A Datasheet(HTML) 38 Page - NEC |
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38 / 56 page  38 µPD178004A, 178006A, 178016A, 178018A (vii) I2C Bus mode (SCL ... internal clock output) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit SCL cycle time tKCY7 R = 1 k Ω 10 µs SCL high-level width tKH7 C = 100 pF Note tKCY7 – 160 ns SCL low-level width tKL7 tKCY7 – 50 ns SDA0, SDA1 setup time (to SCL ↑) tSIK7 200 ns SDA0, SDA1 hold time tKSI7 0ns (from SCL ↓) SDA0, SDA1 output delay time tKSO7 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns (from SCL ↓) 3.5 V ≤ VDD < 4.5 V 0 500 ns SDA0, SDA1 ↓ from SCL↑ or tKSB 200 ns SDA0, SDA1 ↑ from SCL↑ SCL ↓ from SDA0, SDA1↓ tSBK 400 ns SDA0, SDA1 high-level width tSBH 500 ns Note R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line. (viii) I2C Bus mode (SCL ... external clock input) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit SCL cycle time tKCY8 1 000 ns SCL high-/low-level width tKH8, tKL8 400 ns SDA0, SDA1 setup time (to SCL ↑) tSIK8 200 ns SDA0, SDA1 hold time tKSI8 0ns (from SCL ↓) SDA0, SDA1 output delay time tKSO8 R = 1 k Ω 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns from SCL ↓ C = 100 pF Note 3.5 V ≤ VDD < 4.5 V 0 500 ns SDA0, SDA1 ↓ from SCL↑ or tKSB 200 ns SDA0, SDA1 ↑ from SCL↑ SCL ↓ from SDA0, SDA1↓ tSBK 400 ns SDA0, SDA1 high-level width tSBH 500 ns SCL at rising or falling edge time tR8, tF8 1 000 ns Note R and C are the load resistance and load capacitance of SDA0 and SDA1 output line. |
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